Pipeline ADC using Switched Capacitor Sharing Technique with 2.5 V, 10-bit

This paper presents 10-bit, 1.5 MS/s, 2.5V, Low Power Pipeline analog to digital converter using capacitor coupling techniques. A capacitance coupling folded-cascade amplifier effectively saves the power consumption of gain stages of ADC in a 0.25 μm CMOS technology. The ADC also achieves Low power Consumption by the sharing an op-amp between two successive pipeline stage further reduction of power is achieved by removing front end SH circuit from third stage onwards. The ADC, implemented in a 0.25 μm CMOS technology, achieves 10-bit resolution and consumes 13.3 mW power at 5 MHz sampling frequency.